Semiconductor integrated circuits typically are formed by MOS (metal oxide semiconductor) or by bipolar transistors that are integrated at a top planar major surface of a silicon chip. Electrical interconnections between various transistors, as well as between certain transistors and access pins typically located along the periphery of the chip, have typically taken the form of two (or more) "levels" of interconnections, i.e., electrically conducting lines in the form of metallization stripes running along two (or more) essentially planar surfaces that are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Interconnection vias (windows) in the insulating layers are provided whenever they are needed in accordance with the desired circuit interconnections.
In a variety of such integrated circuits--such as random access memories (RAM) and logic circuits--the electrical circuit requires interconnections by means of a number of electrically conducting lines which conveniently are geometrically arranged in the form of an array of mutually parallel metallization stripes. For example, in a DRAM (dynamic RAM) an array of parallel word lines--each word line enabling access to an array of bits, typically hundreds to thousands, by a mutually perpendicular set of bit lines--contains typically hundreds (or more) of parallel word lines. As a consequence, the unavoidable parasitic capacitance across each pair of neighboring word lines gives rise to electrical cross-coupling or "cross-talk" between such word lines, whereby desired electrical access to any given word line, for the purpose of enabling the writing of new information (corresponding to a new word) into the given word line or for reading the existing information (word) stored in the selected line of the memory, results in undesired spurious access to, and consequent spurious writing or reading of information into or out of, the non-accessed neighboring word(s). That is, access to any given word line may spuriously influence the stored charge in the memory cells of the neighboring word line(s) that is (are) supposedly not being accessed. The term "pattern sensitivity" has been applied to this undesirable phenomenon. A similar cross-talk noise problem can be encountered in a parallel array of bit lines. Similarly, in other integrated circuits such as logic circuits, parasitic cross-coupling between neighboring lines--such as lines of a bus, as used for bus-bar routing of interconnections--can give rise to spurious electrical cross-talk between neighboring lines. This cross-talk reduces the sensitivity of the original detection and can result in errors. Accordingly it would be desirable to have an arrangement of lines that avoids such cross-talk.